The present relates to an adaptive equalization and baseline wander correction circuit using halfwave rectifiers and peak detectors with capacitors therein to store DC signals used in the baseline wander correction portion of the circuit and in the adaptive filter portion of the circuit. This sharing of capacitors minimizes the total number of circuit components required.
Adaptive equalization and baseline wander correction circuits are well known in the art. Referring to FIG. 1 there is shown generally an adaptive equalization and baseline wander correction circuit 8 of the prior art. The receiver circuit 8 receives an input signal which is supplied to a first summing circuit 18a, which is one of three summing circuits 18(a-c) shown in FIG. 1. The first summing circuit 18a also receives a signal from the output of a baseline wander correction circuit 20 or DC offset extractor circuit 20, to be discussed later. The output of the first summing circuit 18a is supplied to an adaptive filter 10. The adaptive filter 10 filters the output of the first summing circuit 18a based upon a control signal supplied thereto which is the output of a second summing circuit 18b. The output of the adaptive filter 10 is a signal which is supplied to a third summing circuit 18c. The third summing circuit 18c also receives as an input thereof, the output of the baseline wander correction circuit 20. The output of the third summing circuit 18c is supplied as an input to the baseline wander correction circuit 20 and also as an input to a fullwave rectifier 12.
The output of the fullwave rectifier 12 is supplied to a peak detector 14 and to a slicer 16. The peak detector 14, detects the peak of the rectified signal supplied from the fullwave rectifier 12, and supplies the peak signal to the slicer circuit 16. The output of the peak detector circuit 14 is also supplied to the second summing circuit 18b. The second summing circuit 18b also receives as an input thereof a reference signal. The output of the second summing circuit 18b is supplied as the control signal to the adaptive filter 10.
From the slicer circuit 16, the output is supplied as another input to the baseline wander correction circuit 20. As previously discussed, the baseline wander correction circuit or the DC offset extractor circuit 20 also receives as its input thereof the output of the third summing circuit 18c. The output of the baseline wander correction circuit 20 is supplied as an input to the first and/or third summing circuit 18a and/or 18c, respectively. The output of the slicer circuit 16 is the output of the receiver circuit 8 of FIG. 1.
Referring to FIGS. 2, 3, and 4, there is shown various embodiments of the portions of the receiver circuit 8 shown in FIG. 1. In particular, FIG. 2 shows the circuit diagram of the peak detector circuit 14. FIG. 3 is a circuit diagram of another embodiment of the peak detector 14. FIG. 4 is an embodiment of a baseline wander correction circuit 20.
Although baseline wander correction and adaptive filter circuits are well known in the art, the prior art circuits required many large capacitors and/or large number of digital counters to store extracted DC values for controlling the adaptive filter feedback loop and for correcting the baseline wander DC offset. Thus, the die size has been relatively large.
In the present invention, an improved adaptive equalization and baseline wander correction circuit comprises an adaptive filter means for receiving an input signal and filters the input signal to generate a first signal in response to a control signal. A first halfwave rectifier means receives the first signal and generates a first rectified signal in response thereto. A first peak detector means receives the first rectified signal and generates a first peak signal in response thereto. A signal level extractor means receives the first peak signal and generates a first level signal in response thereto. A low pass filter means receives the first level signal and generates a filtered signal in response thereto. A first summing amplifier means receives the filtered signal and a reference signal and generates a control signal in response thereto. The control signal is the difference of the filtered signal and the reference signal. A second summing amplifier means receives the first signal and a feedback signal and generates a second signal in response thereto. The second signal is the difference of the first signal and the feedback signal. A second halfwave rectifier means receives the second signal and generates a second rectified signal in response thereto. A limiter means receives the first and second rectified signals and generates a third signal in response to the reference signal. A second peak detector means receives the third signal and generates a second peak signal in response thereto. A signal extractor means receives the first and second peak signals and generates a feedback signal. The feedback signal is a DC offset signal of the first and second peak signals. Finally, a slicer means receives the second rectified signal and the filtered signal and generates an output signal in response thereto.